Ferroelectric random access memories (FRAMs) have attracted attention as nonvolatile low-power semiconductor memory devices. As semiconductor memory devices, such as FRAMs, have become more highly integrated, the size of memory cells therein have been reduced using increasingly finer design rules.
U.S. Pat. No. 5,990,507 discusses a method of manufacturing a highly integrated FRAM. In this method, a reflow process is performed on a metal interconnection layer, such as an aluminum layer, in order to form a multi-layered interconnection structure, in which multiple interconnections are electrically connected to one another through a via contact. However, if a reflow process is used to form a via contact for a cell in an FRAM, a spontaneous polarization characteristic of the ferroelectric layer may be degraded.
This potential degradation can be addressed using an etchback process. In particular, after forming a plurality of ferroelectric capacitors on a semiconductor substrate, gap regions between the ferroelectric capacitors are covered with an insulating layer and then planarized using the etchback, such as a dry etch. Thereafter, a local plate line is formed to directly contact the top surfaces of the plurality of capacitors. However, the etchback may remove different amounts of the insulating layer from different regions on a wafer. For example, in a cell array region of an FRAM, more of the insulating layer may be removed near a center of a cell block than at an edge thereof. Thus, a ferroelectric layer under an upper electrode may be exposed due to over-etching or, alternatively, the upper electrode may be not exposed because too little of the insulating layer is removed by the etchback.